1. Field of the Invention
This invention generally relates to a multi-channel dual slope analog-to-digital converting circuit and method thereof, and more particularly to a multi-channel dual slope analog-to-digital converting circuit and method thereof having offset cancellation logic and hysteresis logic.
2. Description of Related Art
A dual slope analog-to-digital converter (ADC) having zero-reset phase is provided in a conventional scheme.
The dual slope ADC uses a correction voltage to eliminate residual offset voltage that is generated during integrating phase and discharge phase. In the conventional scheme, a comparator that is negative feedback connected manages to rapidly reset the output of an integrator, and the correction voltage is stored in the integrating capacitor and another capacitor coupling to the integrating operational amplifier. Where the devices and operation of which scheme is described as follows:FIG. 1 illustrates an offset cancellation circuit diagram of a dual slope ADC. Referring to FIG. 1 herein, the circuit configuration of initialization phase is shown. The offset voltage is stored in the capacitor 102 and all three OPAMPs are set to zero (center) position. This initialization operation is usually referred as Auto Zero operation. Whereas the drawbacks of this conventional scheme are: i. it takes substantially long time to initialize. ii. it requires a substantially large offset cancel capacitor, i.e. large chip area. iii. it has data coupling error or channel coupling error.
Since the capacitor 103 in FIG. 1 is usually a large external capacitor (e.g. >1000 pF) and the resistor 101 has a high resistance in order to generate sufficient time resolution for the dual slope ADC. In the initialization operation, the external capacitor 103 and the offset capacitor 102 are charged through the resistor 101 spontaneously, and thus causing longer initialization period. The output waveform of the integrator during the initialization period following the integrating period, the discharge period, charge reset period is depicted in the diagram of FIG. 11.
On the other hand, the capacitor 102 for the offset cancellation needs to be sufficiently large so that the stored offset voltage is not affected by input gate voltage of the OPAMPs for the integrator 202 and the comparator 203.
This means that a substantially large chip area is required for the offset capacitor 102. Referring to reset period after discharge period as well as auto-zero period shown in FIG. 11.
Moreover, when initialization is not sufficiently long, a residual charge on the external capacitor can affect conversion result to following cycles. An exemplary demonstration is shown in FIG. 11, where residual voltage depends on the initialization period, and the residual voltage affects following conversion cycles.